PIC16F722A-I/SS【PDF 76/286 页】MCU PIC 3.5K FLASH XLP 28-SSOP

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Sheet目录3894

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2010-2012 Microchip Technology Inc.

DS41417B-page 167

PIC16(L)F722A/723A

17.2.4

ADDRESSING

Once the SSP module has been enabled, it waits for a

Start condition to occur. Following the Start condition,

the 8 bits are shifted into the SSPSR register. All incom-

ing bits are sampled with the rising edge of the clock

line (SCL).

17.2.4.1

7-bit Addressing

In 7-bit Addressing mode (Figure 17-10), the value of

ister SSPADD<7:1>. The address is compared on the

falling edge of the eighth clock (SCL) pulse. If the

addresses match, and the BF and SSPOV bits are

clear, the following events occur:

The SSPSR register value is loaded into the

SSPBUF register.

The BF bit is set.

An ACK pulse is generated.

SSP interrupt flag bit, SSPIF of the PIR1 register,

is set (interrupt is generated if enabled) on the

falling edge of the ninth SCL pulse.

17.2.4.2

10-bit Addressing

In 10-bit Address mode, two address bytes need to be

received by the slave (Figure 17-11). The five Most

Significant bits (MSbs) of the first address byte specify

if it is a 10-bit address. The R/W bit of the SSPSTAT

receive the second address byte. For a 10-bit address,

the first byte would equal ‘1111 0 A9 A8 0’, where

A9 and A8 are the two MSbs of the address.

The sequence of events for 10-bit address is as follows

for reception:

Load SSPADD register with high byte of address.

Receive first (high) byte of address (bits SSPIF,

BF and UA of the SSPSTAT register are set).

Read the SSPBUF register (clears bit BF).

Clear the SSPIF flag bit.

Update the SSPADD register with second (low)

byte of address (clears UA bit and releases the

SCL line).

Receive low byte of address (bits SSPIF, BF and

UA are set).

Update the SSPADD register with the high byte

of address. If match releases SCL line, this will

clear bit UA.

Read the SSPBUF register (clears bit BF).

Clear flag bit SSPIF.

If data is requested by the master, once the slave has

been addressed:

Receive repeated Start condition.

Receive repeat of high byte address with R/W = 1,

indicating a read.

BF bit is set and the CKP bit is cleared, stopping

SCL and indicating a read request.

SSPBUF is written, setting BF, with the data to

send to the master device.

CKP is set in software, releasing the SCL line.

17.2.4.3

Address Masking

The Address Masking register (SSPMSK) is only

accessible while the SSPM bits of the SSPCON

select which bits of a received address the hardware

will compare when determining an address match. Any

bit that is set to a zero in the SSPMSK register, the

corresponding bit in the received address byte and

SSPADD register are ignored when determining an

address match. By default, the register is set to all

ones, requiring a complete match of a 7-bit address or

the lower eight bits of a 10-bit address.

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